Redundant Array of Independent Disks (RAID) controller chips use memory blocks for various functions such as data transfer and storage. RAID controllers require some type of non-volatile storage to maintain information such a data cache in the event of power failure. As the RAID controller's primary function is to ensure data coherency, it must be able to preserve the history of all relevant input/output (IO) activity to the storage medium. Typically, this has been done using separate, specialized off-chip RAM components, which increases the overall solution cost. Providing this same capability within the RAID controller itself reduces the overall cost. One current technique for retaining data uses the non-volatile features such as a floating gate process (MNOS—Metal-Nitride-Oxide-Semiconductor) which allows retaining the data while the power is turned off. Another current technique to data retention is known by using the piggy-back battery power up of the Static RAM, such as used in the PC BIOS stand alone chips. However, the standard complementary metal oxide semiconductor (CMOS) technology used by redundant array of independent disks (RAID) input/output (IO) controllers is not amenable to these techniques.
It would be very desirable to have the following features while the RAID controller is powered down: 1) data retained in embedded RAM while the rest of the chip circuitry, such as peripheral drivers/receivers and all core logic, are powered down, 2) maintenance of the stored data in embedded RAM undisturbed during the power-down and power-up of the rest of the chip, and 3) logic circuitry to externally control the states of “sleep” (to power down the I/O and core logic) and “wake” (to resume normal operation).
Therefore, it would be desirable to provide a circuit and method for preventing spurious data from being written to or read from an embedded RAM.